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|Application Note 105
PCB Test – Test bus-connected devices in circuit - isolate them with guard voltages
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|In a bus system, the set of
connecting lines connects all devices on the bus in
parallel. This can make it difficult during pcb testing to pinpoint which
chip is actually faulty. Application of high or low
"guard" voltages can help isolate the device
and disabling devices
|Using guard voltages
ICT fault locators recognise this facility and provide logical high and low guard voltage outputs. Careful placement of guard voltages in a circuit under test can ensure that only the suspect device is enabled.
|Consider the circuit above — suppose you suspect RAM device U3.
U1, U2 and U3 are bus-connected devices sharing address and data buses. In normal operation decoder U4 sets one (and only one) of its outputs low, enabling U1, U2 or U3.
When testing the device with the ICT fault locator, you'll place a test clip, in this case, on U3. When the fault locator tests the device the board is powered up and stimulating signals are applied to the device for a few milliseconds. Because the devices are connected in parallel U1 and U2 are also driven by the fault locator. We can prevent the other devices responding by placing a logic high on each of their CE lines -the devices appear as open circuit to the bus. This process is referred to as guarding. The fault locator includes both logical high and low guard voltages - guard voltages remain at logical high or low for the duration of the test. Other devices on the bus could be similarly disabled - you can apply guard voltages to as many devices as necessary to isolate the device under test. Remember, to test a device you disable all the other parallel devices
Guard voltages can also be used to inhibit clocks and oscillators from producing signals which could appear at the inputs of a device under test. The circuit below is typical of many CPU clock circuits - applying low guard voltages across the crystal as shown will stop the CPU clock.
|Clock signals are often passed
through flip-flops, which serve either as clock frequency
dividers or provide signal shaping or buffering. You can
often prevent the clock signal passing through the
flip-flop by applying a guard voltage to the gating
inputs or SET or RESET lines. If possible, all clocks and
oscillators in a circuit should be disabled during a
test. Careful guarding can get you down to component
Disabling bus buffers
Loop until Pass
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|© Polar Instruments 2002. Polar Instruments pursues a policy of continuous improvement. The specifications in this document may therefore be changed without notice. All trademarks recognised.|