PCB stackup design and tools application notes
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AP517

Specifying high speed PCB stackups appropriately

PCB supply chain managers and procurement engineers sometimes wonder why, even with a fully specified PCB, they receive different builds from different suppliers and even sometimes multiple different builds from the same fabricator. This note describes how Speedstack technical reports deliver flexible and high quality communication for PCB fabricators and brokers, reducing the chances of miscommunication and providing professional stackup documentation from end to end of global and internal supply chains.

AP539

 Choosing reference planes for controlled impedance structures

Polar customers working on stackups sometimes ask "Can I reference a transmission line to a non adjacent plane?" This need can arise when opening an aperture in an adjacent plane above or below the signal line and then referencing to the appropriate plane(s). Speedstack's Advanced Structure Control allows you to reference through mixed planes to non adjacent layers.

AP538

 Predicting the impedance effects of interstitial copper leaves in bookbinder flex

We sometimes get asked about the effects on a structure's impedance from an interstitial copper layer – either from a folded flex or from an interstitial leaf in a bookbinder flex. This note shows how you model the effects of an interstitial copper layer, using one of the multi-dielectric controlled impedance structures in the Si8000m or Si9000e..

Introduction to the Stackup Design System

Using the Stackup Design System

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LIT145
Issue 2

Introduction to controlled impedance PCBs PDF (586k)

Is Controlled Impedance new to you? Then read this helpful booklet first...
(Ideal for color print or on screen viewing)

Printer friendly black and white version PDF (256k)

AP537

PCB Stackup or Buildup – a brief history

Stackup, or buildup of PCBs, has grown in importance over the last decade. This note provides a brief look at how stackups have progressed from the single sided PCB to HDI builds with their multiple layers and multiple passes through the production process.

AP166 V2.0

How is a PCB made and what effects impedance?

(PowerPoint presentation)

Version 2 Now revised and updated to include inner layer and lamination stages

Audience: Will interest you if you want to offer initial training on how PCB fabrication effects impedance, this presentation is valuable to technicians starting training in PCB fabrication, and new designers who need an initial insight into aspects of PCB fabrication. The note is also of interest to companies involved in assembling PCBs as it sheds some light on the processes a PCB undergoes before it is populated.

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AP540

 Corrupted Speedstack configuration file causes an exception error at start up

Occasionally, one or more corrupted Speedstack configuration files may cause a condition where Speedstack displays an exception error when opening a stackup file at startup. This note discusses removing and renewing corrupted configuration files.

AP539

 Choosing reference planes for controlled impedance structures

Polar customers working on stackups sometimes ask "Can I reference a transmission line to a non adjacent plane?" This need can arise when opening an aperture in an adjacent plane above or below the signal line and then referencing to the appropriate plane(s). Speedstack's Advanced Structure Control allows you to reference through mixed planes to non adjacent layers.

AP538

 Predicting the impedance effects of interstitial copper leaves in bookbinder flex

We sometimes get asked about the effects on a structure's impedance from an interstitial copper layer – either from a folded flex or from an interstitial leaf in a bookbinder flex. This note shows how you to model the effects of an interstitial copper layer using one of the multi-dielectric controlled impedance structures in the Si8000m or Si9000e.

AP8189

 Using the Si Projects feature with Speedstack and Si8000m/Si9000e

This note describes how the Si Projects feature incorporated in Speedstack and Si8000m and Si9000e v15.10 and later allows for easy transfer of controlled impedance structures from the Speedstack stackup design tool into the Si8000m and Si9000e field solvers.

AP536

Speedstack material library requirements

Importing material to the Speedstack materials library: Speedstack allows users to add existing material lists to its library; this note describes how to import material data in the format and order used by the Speedstack library.

AP535

Overriding Speedstack library derived dielectric constant values

In most situations it is appropriate to employ the library derived dielectric constant values when adding impedance structures in Speedstack. This note describes how Speedstack 13:06 and onward offers the end user the ability to override the library derived Er on a per structure basis.

AP531

Specifying in-line coupon layout with CGen Coupon Generator

The Polar CGen Coupon Generator includes coupon layout styles that accommodate GGB's SET2DIL Picoprobe; CGen allows for multiple reference and test traces to be arranged in-line to minimise the amount of usable panel consumed by the coupon. This note walks through rapid creation of space optimised insertion loss coupons.

AP527

Professional documentation of low layer count stacks with Speedstack's Virtual Materials Mode

(Powerpoint presentation)

Easy switching between Speedstack's Material Library and Virtual Material modes provides a powerful "freehand" approach to building and experimenting with stackups, allowing you to combine real and virtual materials in the same stack.

AP526

Exploring "What-if" scenarios with Speedstack's Virtual Material Mode

The new Speedstack VMM allows you to experiment with stackup concepts (for example, to examine the effects of different trace widths or dielectric heights) without reference to a materials library. You can pass your completed stack concept to your fabricator for editing with available materials or, for more specialized applications, perform material allocation in house.

AP524

Using Speedflex to document a stack with coated and uncoated areas

This note demonstrate Speedstack's versatility, using the Speedflex Navigator to document a stackup where the board includes areas that are coated with photoresist and surface traces that remain exposed.

AP523

Documenting the press cycles in sequential lamination/HDI with Speedflex Navigator

(PowerPoint presentation 1MB)

A powerful tool for creating and and documenting flex-rigid PCB layer stackups, Speedflex for Speedstack is equally powerful at documenting the press cycles in sequential lamination/HDI.

AP522

Getting started with Speedstack Flex

With Speedstack Flex OEM designers create accurate, efficient, fully documented flex-rigid PCB stackups in just a few minutes. Fabricators can quickly calculate the impact of substituting materials to improve manufacturability and reduce cost while maintaining the specified parameters and performance. In this application note we introduce Speedstack's Flex Navigator and briefly walk through the process of adding a flexible core to a pre-built stack.

Jan 05 CircuiTree article & resources

"Happy Thoughts" - Happy Holden

Specifying controlled impedance & communicating stackups

1 View article: (Happy Thoughts)

2. Stack up file  download (here) - can be viewed in SB200

3. Monte Carlo analysis - (requires a full licence or licensed evaluation of Si8000m) - download (here)

Hint: Once you have downloaded you will need to save the spreadsheet in a suitable folder then open the Si8000 Expert version. Once Excel has loaded open the Monte Carlo spreadsheet - use the F9 key in Excel to run the Monte Carlo analysis for yourself.

Thanks to Westwood PCB for the permission to use the above resources and Circuitree for the article.

AP521

Designer's guide for Printed Circuit Board tolerances

PCBs are made from materials that stretch, shrink, twist and bow. During fabrication laminates are exposed to high temperatures and pressures and many chemical processes; other variables – etch factor, board thickness and dielectric (Er) values must also be taken into account. With these in mind, this note provides some general guidance on tolerances for PCBs.

AP517

Specifying high speed PCB stackups appropriately

PCB supply chain managers and procurement engineers sometimes wonder why, even with a fully specified PCB, they receive different builds from different suppliers and even sometimes multiple different builds from the same fabricator. This note describes how Speedstack technical reports deliver flexible and high quality communication for PCB fabricators and brokers, reducing the chances of miscommunication and providing professional stackup documentation from end to end of global and internal supply chains.

AP511

Verifying stack design with Speedstack 2008

PCB designers often wish to verify that the stack design to be sent to a PC fabrication company is manufacturable. Speedstack 2008, with its  "Remake Stack with Autostack" facility, makes it easy for PCB designer and fabricator to share builds and verify that the stack can be realised with the fabricator's available materials.

AP510

Redesigning stacks for lead-free builds with Speedstack 2008

A common challenge for PCB fabricators is taking an existing FR4 stack and redesigning it for lead- free builds. Speedstack 2008 offers a powerful and automatic solution to this tedious process. In this note we change the core and prepreg materials from standard FR4 to material with a higher performance with only a few mouse clicks. 

AP509

How to check for resin starvation by using the DRC Excess Resin test in Speedstack

Polar's Speedstack PCB Stackup Builder incorporates a comprehensive Design Rules Check (DRC) function that includes checks for symmetry, copper balance, minimum trace and gap widths and excess resin, etc. Values for excess resin may be added to the material libraries for prepregs. This application note discusses how to calculate the excess resin value for the Polar Speedstack library field.

AP507b

Base thickness and isolation dimension definitions

(PowerPoint presentation)

This short note provides a graphical explanation of base thickness, finished thickness and isolation distance as used in Speedstack.

AP507

Calculating dielectric height with Speedstack

Speedstack is fully integrated with the Si8000 Controlled Impedance Quick Solver/Si9000 PCB Transmission Line Field Solver to allow easy addition of controlled impedance structures to  layers in the stackup. The H Value (the effective height of a dielectric substrate after the pressing of the stack) calculation produces the dielectric heights required for the Polar SI8000/9000 field solvers.

AP505

SB200 - New from v5.1  Symmetrical Build slashes stackup creation time in half

(PowerPoint presentation)

The SB200 Symmetrical Build function provides dramatic reductions in stackup creation time. With just a few mouse clicks you can create a design-rule checked symmetrical stackup in minutes.  

AP503

Offset stripline - construction matters

(PowerPoint presentation)

Calculating impedance accurately on striplines depends on the relative positions of prepreg and core in the stack. This presentation explains graphically how to ensure your calculations are as accurate as possible.(Download)

AP179

Transferring controlled impedance parameters between the SB200 and the Si8000

The SB200 incorporates the facility to add controlled impedance structures to a layer in the stackup. Structure parameters may be copied to the Si8000 Quick Solver for processing (for example by the Si8000 Goal Seeking function) and calculated values pasted back to the SB200 for insertion into the stackup.

This application note outlines the process of exchanging controlled impedance parameters between the SB200 and the Si8000 to add a controlled impedance structure with the correct impedance value to a stackup layer.

AP178

Updating Si8000m to interface with SB200a Professional Edition

The new SB200a Professional edition is designed to communicate and share layer stackup information with the Si8000m controlled impedance field solver. Together they form a powerful unified system for documentation and design of complex high speed PCB layer stackups and associated transmission line structures.

To realise communication between the two packages Si8000m existing customers need to update to Si8000 Version 3.00 or above.  Version 3.xx includes the links between the two products and supports some additional typical impedance controlled structures for multiple dielectric stackups.