Speedstack Si – Insertion loss controlled PCB stackup design system

Speedstack Si with full insertion loss documentation and design parameters includes Cannonball-Huray modeling of surface roughness

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Speedstack Si – Stackup design for impedance & insertion loss controlled PCBs

Speedstack Si insertion loss controlled PCB stackup design tool is made for you if you are a designer, fabricator or PCB technologist who needs to manage PCB stackups with both impedance and insertion loss control. In addition to incorporating Polars proven insertion loss field solver capability, Speedstack Si allows rapid import and export of insertion loss projects into the Si9000e insertion loss field solver so you can analyse your stack up design in detail.

Speedstack Si delivers rich reporting capability and not only generates the stackup material data but also graphs predicted insertion loss characteristics – including industry standard modeling for roughness using Hammerstad, Groisse and Cannonball-Huray methods.

Speedstack Si license holders have full access to the stand alone Si9000e Quick Solver license. The designer or board fabricator can use the Goal Seek facility of the Si9000e field solver to arrive rapidly at the controlled impedance structure parameters to produce the target impedance. Speedstack Si is able to directly output controlled impedance test files associated with each stackup for use with the Polar CITS series of TDR impedance testers.

Optional rapid modelling of both rigid and flex-rigid stackups with Speedstack Flex

Speedstack Si provides an intuitive graphical interface to allow designers to create accurate and efficient stackups for both rigid and flex-rigid PCBs with minimum effort, producing error-free documentation for tighter control over the finished board. For PCB fabricators, Speedstack Si allows experimentation with alternative materials to provide high manufacturability at minimum cost while maintaining the specified parameters and performance of the board.

Speedstack navigator for multiple cross sections with both Speedstack HDI and Speedstack Flex option

The Navigator provides a clear contextual view of the rigid and flexible stacks within a flex-rigid build and allows easy alignment of displayed materials between stacks.

The associated technical report also supports different materials on the same dielectric layer, improving the clarity of documentation between the stackup designer and fabricator. For the OEM this offers a clear method of sending impedance test specifications out to suppliers or brokers.

Designers and fabricators can work together and select the best material combinations for minimising build costs. Fabricators can share their in house material libraries with OEMs and ensure the most effective material choice is employed in the build.

For flex-rigid and HDI stackups – also see Speedstack Flex and Speedstack HDI

Watch the build of a sequential lamination PCB on the Polar YouTube channel

A brief YouTube presentation shows you just how easy it is to document sequential lamination with Speedstack HDI.

Watch the presentation here

Speedstack Si is ideal for you if:

• You need to calculate impedance requirements and model loss on multilayer boards with multiple controlled impedance structures per stack.

• You need to extract engineering information to drive simulation software prior to committing a design into production.

• You need to alter line widths and rapidly communicate the new build information electronically.

• You need to experiment with differing stack up approaches – for example, you can substitute material because of a shortage and rapidly check the new overall height, line width and transmission line impedance values. By employing the link between the Si9000e transmission line design system and Speedstack software you can recalculate all the impedance values in a single pass in a fraction of the time taken traditionally.

Speedstack provides data exchange with the companies below

Speedstack Si includes Speedstack and Si9000e

License options

Request a Speedstack Si evaluation

Feature request policy and process