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| PCB stackup design and tools application notes | |
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What's new? |
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Need to model insertion loss owing to Cu roughness but don’t have access to SEM data? Simonovich-Cannonball is an effective preprocessor to enable engineers with access to Rz roughness figures to use Huray models for roughness losses when access to scanning electron microscope data is not available. This note contains links to two white papers by Bert Simonovich of LamSim Enterprises: Practical Method for Modeling Conductor Surface Roughness Using The Cannonball Stack Principle Heuristic Modeling of Transmission Lines due to Mixed Reference Plane Foil Roughness |
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How to calculate Surface and Coated Structures on the same stackup In some instances it may be required to have a coated and non-coated structure on the same stack up. This note discusses one way to achieve this and references another AP for an alternative approach. |
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Multi-user usage of SpeedStack, Si8000m, Si9000e and CGen software Explains how Polar software segregates the configuration settings when multiple users use the same device (locally or remotely). |
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Speedstack library filter commands explained Using the Material Library filtering to find specific materials or parameters is explained so that complex search criteria can be build and saved for future reference. |
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Goal seeking target impedance with W1/W2 Constant Pitch Sometimes when specifying controlled impedance structures using Si8000m / Si9000e / Speedstack you need to goal seek a target impedance, varying trace width while holding the trace pitch constant. This note discusses trace pitch and W1/W2 Constant Pitch Goal Seek option |
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Accessing the Polar Speedstack online material libraries via a proxy server Speedstack versions 17.05 and later include the Polar Online Material Library. This note explains how, if your organisation connects to the internet via a proxy server, you may need to ask your MIS department to grant permission to bypass the proxy server to access the library. |
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Obtaining the Polar Speedstack material libraries for on-premise use When a local copy of the Online Material Library is required, Speedstack allows a complete set of all libraries to be downloaded to a local folder. Where access to the Online Material Library is unavailable or prohibited, a copy of the online library may be obtained on request to Polarcare subscribers; this note describes how to acquire and install the set of material libraries for local (on-premise) access. |
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Back drilling PCBS for signal integrity with Speedstack 2020 Can't view the video? Click here |
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Using mini-stacks in Speedstack in rigid-flex constructions Speedstack supports bookbinder flex constructions, in which a stacked pair of flex sections links the two rigid sections of the flex-rigid construction. Speedstack allows the flex sub-stack to be defined as a single stack construction with two flex cross-sections separated by an air gap or as two individual mini-stacks. This note illustrates how to use Speedstack's Structure Control dialog to add controlled impedance structures based on the designer's defined arrangement of signal layers and reference planes. |
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Building a rigid-flex construction with Speedstack Speedstack Navigator's graphical interface simplifies the creation of complex multi stack constructions; this allows PCB fabricators and OEM engineers rapidly to create and document accurate and efficient flex-rigid PCB layer stackups. Navigator functions include the ability to add, delete and edit sub-stacks. This note walks through the construction of a rigid-flex-rigid stackup. |
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Documenting differential pairs without underlying ground planes for Gigabit Ethernet routing in Speedstack Occasionally there are applications where a ground plane below a differential pair is undesirable. This application note explains how to model and document this scenario in any situation where the differential pair needs to be a “pure” differential implementation (100% of the signal and return being carried by the pair rather than partially returned through an underlying ground.) |
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Choosing reference planes for controlled impedance structures Polar customers working on stackups sometimes ask "Can I reference a transmission line to a non adjacent plane?" This need can arise when opening an aperture in an adjacent plane above or below the signal line and then referencing to the appropriate plane(s). Speedstack's Advanced Structure Control allows you to reference through mixed planes to non adjacent layers. |
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Building a PCB stackup with Speedstack Speedstack is a comprehensive PCB stackup design environment for pre-layout engineers, PCB fabricators and value-add PCB brokers. This Getting Started tutorial will familiarize you with the features and operation of Polar’s Speedstack PCB Stackup Builder and guide you through the steps to create a Speedstack project (.sci) file. Download the project file for reference and help in creating your own |
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LIT145 |
Introduction to controlled impedance PCBs – PDF (586k) Is Controlled Impedance new to you? Then read this helpful booklet first... Printer friendly black and white version PDF (256k) |
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PCB Stackup or Buildup – a brief history Stackup, or buildup of PCBs, has grown in importance over the last decade. This note provides a brief look at how stackups have progressed from the single sided PCB to HDI builds with their multiple layers and multiple passes through the production process. |
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AP166 V2.0 |
How is a PCB made and what effects impedance? Version 2 Now revised and updated to include inner layer and lamination stages Audience: Will interest you if you want to offer initial training on how PCB fabrication effects impedance, this presentation is valuable to technicians starting training in PCB fabrication, and new designers who need an initial insight into aspects of PCB fabrication. The note is also of interest to companies involved in assembling PCBs as it sheds some light on the processes a PCB undergoes before it is populated. |
Need to model insertion loss owing to Cu roughness but don’t have access to SEM data? Simonovich-Cannonball is an effective preprocessor to enable engineers with access to Rz roughness figures to use Huray models for roughness losses when access to scanning electron microscope data is not available. This note contains links to two white papers by Bert Simonovich of LamSim Enterprises: Practical Method for Modeling Conductor Surface Roughness Using The Cannonball Stack Principle Heuristic Modeling of Transmission Lines due to Mixed Reference Plane Foil Roughness |
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Speedstack library filter commands explained Using the Material Library filtering to find specific materials or parameters is explained so that complex search criteria can be build and saved for future reference. |
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Goal seeking target impedance with W1/W2 Constant Pitch Sometimes when specifying controlled impedance structures using Si8000m / Si9000e / Speedstack you need to goal seek a target impedance, varying trace width while holding the trace pitch constant. This note discusses trace pitch and W1/W2 Constant Pitch Goal Seek option |
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Obtaining the Polar Speedstack material libraries for on-premise use When a local copy of the Online Material Library is required, Speedstack allows a complete set of all libraries to be downloaded to a local folder. Where access to the Online Material Library is unavailable or prohibited, a copy of the online library may be obtained on request to Polarcare subscribers; this note describes how to acquire and install the set of material libraries for local (on-premise) access. |
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Using mini-stacks in Speedstack in rigid-flex constructions Speedstack supports bookbinder flex constructions, in which a stacked pair of flex sections links the two rigid sections of the flex-rigid construction. Speedstack allows the flex sub-stack to be defined as a single stack construction with two flex cross-sections separated by an air gap or as two individual mini-stacks. This note illustrates how to use Speedstack's Structure Control dialog to add structures based on the designer's defined arrangement of signal layers and reference planes. |
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Building a rigid-flex construction with Speedstack Speedstack Navigator's graphical interface simplifies the creation of complex multi stack constructions; this allows PCB fabricators and OEM engineers rapidly to create and document accurate and efficient flex-rigid PCB layer stackups. Navigator functions include the ability to add, delete and edit sub-stacks. This note walks through the construction of a rigid-flex-rigid stackup. |
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Documenting differential pairs without underlying ground planes for Gigabit Ethernet routing in Speedstack Occasionally there are applications where a ground plane below a differential pair is undesirable. This application note explains how to model and document this scenario in any situation where the differential pair needs to be a “pure” differential implementation (100% of the signal and return being carried by the pair rather than partially returned through an underlying ground.) |
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Accessing the Polar Speedstack online material libraries via a proxy server Speedstack versions 17.05 and later provide access to the Polar Online Material Library. This note explains how, if your organisation connects to the internet via a proxy server, you may need to ask your MIS department to grant permission to bypass the proxy server to access the library. |
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Corrupted Speedstack configuration file causes an exception error at start up Occasionally, one or more corrupted Speedstack configuration files may cause a condition where Speedstack displays an exception error when opening a stackup file at startup. This note discusses removing and renewing corrupted configuration files. |
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Choosing reference planes for controlled impedance structures Polar customers working on stackups sometimes ask "Can I reference a transmission line to a non adjacent plane?" This need can arise when opening an aperture in an adjacent plane above or below the signal line and then referencing to the appropriate plane(s). Speedstack's Advanced Structure Control allows you to reference through mixed planes to non adjacent layers. |
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Predicting the impedance effects of interstitial copper leaves in bookbinder flex We sometimes get asked about the effects on a structure's impedance from an interstitial copper layer – either from a folded flex or from an interstitial leaf in a bookbinder flex. This note shows how you to model the effects of an interstitial copper layer using one of the multi-dielectric controlled impedance structures in the Si8000m or Si9000e. |
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Using the Si Projects feature with Speedstack and Si8000m/Si9000e This note describes how the Si Projects feature incorporated in Speedstack and Si8000m and Si9000e v15.10 and later allows for easy transfer of controlled impedance structures from the Speedstack stackup design tool into the Si8000m and Si9000e field solvers. |
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Speedstack material library requirements Importing material to the Speedstack materials library: Speedstack allows users to add existing material lists to its library; this note describes how to import material data in the format and order used by the Speedstack library. The note discusses importing materials both from the online library and from local material files and filtering materials by supplier and by the specfied frequency of measurement of dielectric constant and loss tangent. |
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Overriding Speedstack library derived dielectric constant values In most situations it is appropriate to employ the library derived dielectric constant values when adding impedance structures in Speedstack. This note describes how Speedstack 13:06 and onward offers the end user the ability to override the library derived Er on a per structure basis. |
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Specifying in-line coupon layout with CGen Coupon Generator The Polar CGen Coupon Generator includes coupon layout styles that accommodate GGB's SET2DIL Picoprobe; CGen allows for multiple reference and test traces to be arranged in-line to minimise the amount of usable panel consumed by the coupon. This note walks through rapid creation of space optimised insertion loss coupons. |
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Professional documentation of low layer count stacks with Speedstack's Virtual Materials Mode (Powerpoint presentation) Easy switching between Speedstack's Material Library and Virtual Material modes provides a powerful "freehand" approach to building and experimenting with stackups, allowing you to combine real and virtual materials in the same stack. |
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Exploring "What-if" scenarios with Speedstack's Virtual Material Mode The new Speedstack VMM allows you to experiment with stackup concepts (for example, to examine the effects of different trace widths or dielectric heights) without reference to a materials library. You can pass your completed stack concept to your fabricator for editing with available materials or, for more specialized applications, perform material allocation in house. |
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Using Speedflex to document a stack with coated and uncoated areas This note demonstrate Speedstack's versatility, using the Speedflex Navigator to document a stackup where the board includes areas that are coated with photoresist and surface traces that remain exposed. |
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Documenting the press cycles in sequential lamination/HDI with Speedflex Navigator (PowerPoint presentation 1MB) A powerful tool for creating and and documenting flex-rigid PCB layer stackups, Speedflex for Speedstack is equally powerful at documenting the press cycles in sequential lamination/HDI. |
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Getting started with Speedstack Flex With Speedstack Flex OEM designers create accurate, efficient, fully documented flex-rigid PCB stackups in just a few minutes. Fabricators can quickly calculate the impact of substituting materials to improve manufacturability and reduce cost while maintaining the specified parameters and performance. This application note introduces Speedstack's Flex Navigator and briefly walks through the process of adding a flexible core to a pre-built stack. |
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Jan 05 CircuiTree article & resources |
"Happy Thoughts" – Happy Holden Specifying controlled impedance & communicating stackups 1. View article: (Happy Thoughts) 2. Stack up file (download) – can be viewed in Speedstack 3. Monte Carlo analysis (requires a full licence or licensed evaluation of Si8000m) (download) Hint: Once you have downloaded you will need to save the spreadsheet in a suitable folder then open the Si8000 Expert version. Once Excel has loaded, open the Monte Carlo spreadsheet – use the F9 key in Excel to run the Monte Carlo analysis for yourself. |
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Designer's guide for Printed Circuit Board tolerances PCBs are made from materials that stretch, shrink, twist and bow. During fabrication laminates are exposed to high temperatures and pressures and many chemical processes; other variables – etch factor, board thickness and dielectric (Er) values must also be taken into account. With these in mind, this note provides some general guidance on tolerances for PCBs. |
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Specifying high speed PCB stackups appropriately PCB supply chain managers and procurement engineers sometimes wonder why, even with a fully specified PCB, they receive different builds from different suppliers and even sometimes multiple different builds from the same fabricator. This note describes how Speedstack technical reports deliver flexible and high quality communication for PCB fabricators and brokers, reducing the chances of miscommunication and providing professional stackup documentation from end to end of global and internal supply chains. |
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How to check for resin starvation by using the DRC Excess Resin test in Speedstack Polar's Speedstack PCB Stackup Builder incorporates a comprehensive Design Rules Check (DRC) function that includes checks for symmetry, copper balance, minimum trace and gap widths and excess resin, etc. Values for excess resin may be added to the material libraries for prepregs. This application note discusses how to calculate the excess resin value for the Polar Speedstack library field. |
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Base thickness and isolation dimension definitions (PowerPoint presentation) This short note provides a graphical explanation of base thickness, finished thickness and isolation distance as used in Speedstack. |
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Calculating dielectric height with Speedstack Speedstack is fully integrated with the Si8000 Controlled Impedance Quick Solver/Si9000 PCB Transmission Line Field Solver to allow easy addition of controlled impedance structures to layers in the stackup. The H Value (the effective height of a dielectric substrate after the pressing of the stack) calculation produces the dielectric heights required for the Polar SI8000/9000 field solvers. This note explains the terms dielectric height and isolation distance. |
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Symmetrical Build slashes stackup creation time in half (PowerPoint presentation) The Speedstack Symmetrical Build function provides dramatic reductions in stackup creation time. With just a few mouse clicks you can create a design-rule checked symmetrical stackup in minutes. |
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Offset stripline – construction matters (PowerPoint presentation) Calculating impedance accurately on striplines depends on the relative positions of prepreg and core in the stack. This presentation explains graphically how to ensure your calculations are as accurate as possible. (Download) |
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Transferring controlled impedance parameters between the Speedstack and the Si8000 Speedstack incorporates the facility to add controlled impedance structures to a layer in the stackup. Structure parameters may be copied to the Si8000 Quick Solver for processing (for example by the Si8000 Goal Seeking function) and calculated values pasted back to Speedstack for insertion into the stackup. This application note outlines the process of exchanging controlled impedance parameters between Speedstack and the Si8000 to add a controlled impedance structure with the correct impedance value to a stackup layer. |
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