Product information
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CITS880s & TRC Plus – accurate
measurements on fine line traces
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![](images/Si8000m_crosstalk_tmb.jpg)
Si8000m / Si9000e Field Solver – differential pair crosstalk
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![](images/si9000_graph_tmb.jpg)
Si9000e graphing, roughness goal seek, sensitivity analysis projects, trace resistance vs temperature
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![Si8000m / Si9000e Monte_Carlo impedance simulation](images/monte_carlo_tmb.jpg)
Si8000m / Si9000e Monte Carlo impedance simulation
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Webinar Nov 2020 – Introduction to Insertion Loss
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![Atlas Delta-L PCB Insertion Loss Test](images/Atlas_loss.jpg)
Atlas Delta-L PCB Insertion Loss Test System
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CGen PCB Impedance and Insertion loss Coupon Generator
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Atlas for Anritsu ShockLine™ Delta L 4.0 Eigenvalue Insertion Loss Test
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CITS880s – Controlled Impedance
Test System
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![Si8000m_sensitivity analysis](images/speedstack_intro_tmb.jpg)
Speedstack PCB stackup design and documentation
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![Toneohm 950](images/Toneohm_950.jpg)
Find ground plane shorts with the
Toneohm 950 multi-layer short
circuit locator
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![](images/si9000_graph_tmb.jpg)
Si9000e graphing, roughness goal seek, sensitivity analysis projects, trace resistance vs temperature
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How to...
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Anatomy of a PCB impedance test
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Create impedance coupons efficiently with Speedstack & CGEN
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Create impedance coupons with Si8000m / Si9000e & CGEN
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CITS880s – getting started with controlled impedance testing
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Inserting controlled impedance tests with the CITS880s Setup Wizard
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Data logging with the CITS880s Controlled Impedance Test System
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Si8000m / Si9000e – importing measurement impedance from CITS
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![Si8000m Si9000e Crosstalk](images/Si8000m_crosstalk_tmb.jpg)
Si8000m / Si9000e Field Solver – differential pair crosstalk
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![](images/Compare_predicted_and_measured_impedance_tmb.jpg)
Si8000m – how to compare measured with modeled impedance
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![CGen mixed layers](images/stop_resistance_clouding_tmb.jpg)
Removing DC trace resistance errors from characteristic impedance measurements
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![How to compare modeled with measured impedance](images/Si9000_VNA_tmb.jpg)
Si9000e – compare modelled insertion loss with VNA measurement
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![](images/vm_lm_modes_tmb.jpg)
Using Speedstack Virtual Material
and Material Library modes |
![Online_library](images/polar_online_library_tmb.jpg)
Downloading Polar Speedstack
online material libraries
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![](images/align_materials_tmb.jpg)
Aligning flex and rigid materials in the Speedstack Navigator
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![CGen mixed layers](images/CGen_2020_tmb.jpg)
Using CGen PCB Coupon Generator with mixed layer types
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Si8000m / Si9000e
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Coming soon....
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![Si8000m_sensitivity analysis](images/S-parameter_Alias.jpg)
Spotting and solving alias effects in s-parameters
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![Si8000m_getting_started](images/Si8000m_getting_started_tmb.jpg)
Si8000m – getting started with controlled impedance modelling
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![Si8000m_sensitivity analysis](images/si8000m_sens_anal_tmb.jpg)
Si8000m / Si9000e – getting started with sensitivity analysis
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![Si8000m process window](images/si8000m_process_window_tmb.jpg)
Si8000m – sensitivity analysis – exploring the process window
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![Si8000m / Si9000e Monte_Carlo impedance simulation](images/monte_carlo_tmb.jpg)
Si8000m / Si9000e Monte Carlo impedance simulation
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![Si9000e_Capacitance_options](images/si9000e_capacitance_tmb.jpg)
Si9000e Field Solver capacitance options
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![](images/Si8000m_crosstalk_tmb.jpg)
Si8000m / Si9000e Field Solver – differential pair crosstalk
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![How to compare modeled with measured impedance](images/Si9000_VNA_tmb.jpg)
Si9000e – compare modelled insertion loss with VNA measurement
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![](images/si9000_graph_tmb.jpg)
Si9000e graphing, roughness goal seek, sensitivity analysis projects, trace resistance vs temperature
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Speedstack PCB
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![Si8000m_sensitivity analysis](images/speedstack_intro_tmb.jpg)
Speedstack PCB stackup design and documentation
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![Online_library](images/material_partner_tmb.jpg)
Working with Polar Speedstack
library material partners
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![Online_library](images/polar_online_library_tmb.jpg)
Downloading Polar Speedstack
online material libraries
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![IPC2581 import/export](images/IPC2581_tmb.jpg)
IPC2581 import/export
Using on-premise material libraries
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![](images/back_drilling_tmb.jpg)
Back drilling PCBs for
signal integrity
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![](images/ipc_plating_tmb.jpg)
Adding IPC class
documentation in Speedstack
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![Net classes](images/net_cls_IO_tmb.jpg)
Speedstack – Import/export options and Net classes
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Speedstack documents
shield materials
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![Speedstack library filtering](images/Speedstack_2023_filtering_sml.jpg)
Speedstack PCB Filtering Options
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Speedstack Si
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![](images/speedstack_si_tmb.jpg)
Speedstack Si 2018 Intro - plus Cannonball-Huray enhancement
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![](images/finetune_projects_tmb.jpg)
Fine tuning PCB stackups
with Si Projects
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![](images/drills_vias.jpg)
Speedstack Si – loss modelling and new via fill types
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![](images/si9000_insertion_loss_roughness_tmb.jpg)
Speedstack-Si9000e insertion loss – roughness modelling
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Speedstack Flex
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![](images/speedstack_flex_tmb.jpg)
Design and document flex-rigid stackups with Speedstack Flex
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![](images/multi_select_tmb.jpg)
Selecting multiple materials in
Speedstack Flex
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![](images/diag_sym_flex_tmb.jpg)
Documenting a flex-rigid stack with diagonal symmetry
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![](images/align_materials_tmb.jpg)
Aligning flex and rigid materials in the Speedstack Navigator
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Speedstack HDI
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![](images/sequential_plan.jpg)
Documenting sequential lamination
in Speedstack HDI
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![](images/coated_uncoated_tmb.jpg)
Adding coated and uncoated microstrips in Speedstack HDI
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![](images/unlimited_drills_tmb.jpg)
Adding unlimited drills with
Speedstack HDI
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