PCB controlled impedance / PCB signal integrity application notes

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Comparing Polar grounded and fixed and variable pitch groundless differential probes

Polar groundless differential probes are especially designed for on board test of differential traces where direct access to the ground plane is difficult or impossible. They are available as both fixed pitch and variable pitch to accommodate a wide variety of footprints. This note illustrates the excellent correspondence between the grounded and fixed and variable pitch groundless probe varieties.


Operating principle of groundless differential probes for CITS880s

Polar series of GDPS (groundless diferential) probes provides a measurement solution for situations where there is no physical access to the ground plane, or where a ground plane is not present. This note introduces the GDPS probe.


Polar GDPS groundless differential probes for on board impedance testing

Polar GDPS probes are designed to allow the CITS880s (v15.01 or later) to measure the impedance of balanced differential traces without the need to make a ground connection to the board or coupon under test. This is an ideal compromise for situations where access to the ground plane of the pcb is impracticable or for situations where you need to test a balanced differential pair such as a broadside coupled surface trace on a flex circuit.


Introduction to Controlled Impedance

Controlled Impedance Design and Test

Controlled Impedance Theory

Using the Si8000.

Using the CITS

Using the Si6000. Legacy Product index

Si6000 sample workbooks. Legacy Product index

 Is Controlled Impedance new to you? Then read this helpful booklet first...


Issue 2

Introduction to controlled impedance PCBs

PDF (586k) Ideal for color print or on screen viewing

Printer friendly black and white version 



How is a PCB made and what effects impedance?

Powerpoint presentation. Download .zip file

Version 2 – Now revised and updated to include inner layer and lamination stages

Audience: Will interest you if you want to offer initial training on how PCB fabrication affects impedance; this presentation is valuable to technicians starting training in PCB fabrication and new designers who need an initial insight into aspects of PCB fabrication. The note is also of interest to companies involved in assembling PCBs as it sheds some light on the processes a PCB undergoes before it is populated.


Controlled Impedance Test 

Key to producing good yields of high-quality PCBs is the relationship between the circuit designer, PCB layout engineer and front-end process engineers at the PCB fabricator. Accurate, traceable and repeatable test results are essential to feeding production data back into the production process in order to increase yields and lower unit costs.

"The Board Authority" article reprint (with thanks to Circuitree Magazine) 


Introducing Controlled Impedance

PowerPoint presentation (no previous electronics knowledge required)

Right click the link, then choose "Save Target As..." to download. 

Free Powerpoint viewer


Frequently Asked Questions on Controlled Impedance

Controlled impedance traces have started to move from purely specialist applications into more commonplace use during the last few years. Here are some answers to questions most frequently asked of Polar.


Introduction to Controlled Impedance

As PCB signal switching speeds increase today's PCB designer needs to understand and control the impedance of PCB traces. So what is controlled impedance and why do we need to control PCB trace impedance?


Transmission Line Configurations

Short signal transition times and high clock rates mean that today's PCB traces need to be considered as transmission lines. In this application note we look at two configurations of transmission line and see what determines the characteristic impedance of a PCB trace.


Microstrip Transmission Line Structures

Today's high performance PCB traces are manufactured as transmission lines in microstrip or stripline construction. In this application note we look at several microstrip transmission line structures.


Single-ended Stripline Structures

In this application note we look at the single-ended stripline structure — a line embedded in a dielectric between two reference planes — one of the two most popular constructions of transmission lines on PCBs.


Odd mode and even mode impedance — an introduction

An increasing number of designs (for example USB 2.0) calls for control of both odd and even mode impedance. This note briefly discusses signals and termination on coupled lines, and the importance of even and odd mode impedance.


Effective Er — why effective Er is not the same as bulk Er.

Over simplified modelling of differential structures can lead to discrepancies of several ohms in controlled impedance calculations. This note explains why local variations in Er within a dielectric can lead to unexpected results. 

Power point presentation (~900KB). 

Free Powerpoint viewer


Uncontrolled Impedance Tracks: Maximum Length Calculator

Microsoft Excel workbook (~16KB)

When the length of a signal trace exceeds the quarter-risetime distance (1/4 of the distance a signal can travel in your logic device risetime) you should probably consider using controlled impedance traces.

Use the controls on this worksheet to determine the quarter-risetime distance of your system using your logic devices.

Note: This spreadsheet contains macro controls, you will need to set Excel's Tools Macro: Security: to Medium and when opening the file click on Enable Macros



Comparing Polar grounded and fixed and variable pitch groundless differential probes

Polar groundless differential probes are especially designed for on board test of differential traces where direct access to the ground plane is difficult or impossible. They are available as both fixed pitch and variable pitch to accommodate a wide variety of footprints. This note illustrates the excellent correspondence between the grounded and fixed and variable pitch groundless probe varieties.


Economics of PCB impedance test and the hidden cost of reducing rise time

From the early days of impedance controlled PCBs OEMs and PCB fabricators have expressed the need to test on short traces and test using fast rise times and in appropriate situations this can be true, but in the headlong push for speed the hidden running costs are often overlooked in the rush for risetime. This note looks at the real costs of testing short traces with fast rise time TDRs and provides some useful rules of thumb for choosing measurement techniques and equipment.


RIE loss / attenuation measurement method and PCB manufacture

This application note provides a brief introduction to RIE (Root Impulse Energy) testing, one of 4 PCB material loss (attenuation) measurement methods shortly to be published by IPC. RIE testing is aimed at the PCB manufacturing shop floor to provide an easily deployed and relatively straight-forward method of monitoring the high frequency performance of PCBs to ensure they stay within an acceptable loss budget.


Vias, stubs and minimizing their visibility to high speed signals

Many of our PCB design customers ask us about modelling plated through hole (PTH) vias with respect to impedance. However, from a signal integrity standpoint, unconnected via stubs have a far larger effect on the signal than the geometry of the via itself. This note explains how the Polar Si9000 can help you check if, at your desired bit rate or operating frequency, you need to take steps to reduce or remove the effects of via stubs. 


An introduction to forward and reverse crosstalk

Crosstalk is the unwanted coupling of energy between two or more adjacent lines. The electromagnetic fields between two closely coupled lines interact with each other and will affect the behaviour of the signals on both lines. This note discusses near and far-end crosstalk and includes formulas that will enable the maximum peak effect to be predicted.


Testing the precision cables on the Polar CITS900

After extensive use the flexible cables used with the CITS900 will deteriorate and this will ultimately affect measurements made. This application note is intended to help owners of the CITS900 to check on the condition of the flexible test cables and decide when to replace.


Impedance correlation requirements

Occasionally, measured and predicted impedance do not correlate with expected measurement. Polar offers a professional commercial correlation service to help determine the root cause of the variation. Correlation services are chargeable, and are available for correlation questions arising on impedance controlled structures modelled with Si8000m and measured with CITS500s (32bit) or CITS800s. This application note details the physical and technical documentation required for a correlation study.


Nickel-gold plating copper PCB traces

Nickel plating of copper PCB traces, widely practised in the microwave industry, is acceptable on short lengths of pad to accommodate gold plating; plating the whole trace length is generally not a good idea. This application note explains the effect that nickel will have on high frequency transmission lines.


Locating Critical Tracks on PCB Inner Layers

From susceptibility to electrical interference to control of track cross-sectional dimensions — this note provides several good reasons why you shouldn’t put critical tracks on the surface layer of a PCB.


Transmission line testing — VNA or TDR?

Sometimes board fabricators are asked to test PCB transmission lines at a given frequency.  In some cases boards are tested using a Vector Network Analyser (VNA) and in others a Time Domain Reflectometer (TDR); both instruments should offer similar readings. This note sets out to explain expected differences in measurement results, and points out where differences are due to incorrect test setup rather than any material problem.


Top 12 reasons for specifying DC track resistance.

DC Track resistance is increasingly being specified on PCBs, here are some of the reasons that engineers point out to us why they needing to know and control DC trace resistance...


Modelling a Broadside Coupled Differential Pair without Ground

The Si8000 does not include the Broadside Coupled Differential Pair without Ground structure; this application note describes how the Surface Microstrip structure may be utilised to provide a workable solution.


Measurement of Track Resistance

Track resistance is usually much less than one ohm, often less than 0.1 ohm. The connection between a probe and the track surface can easily reach or exceed the track resistance; this application note describes how the associated measurement errors can be reduced using "Four Terminal" or "Kelvin Sensing" techniques.


Calculating Track Resistance

It is sometimes necessary to know the DC resistance of a track; this application note briefly describes how simple formulas may be used to derive track resistance.


Unbalanced Tracks and Differential Impedance

PDF version (29k)

To obtain a particular value of differential impedance, the two signal tracks are usually assumed to have the same cross-section — the balanced track case, used in most impedance calculation software. However, due to manufacturing techniques and tolerances, the two tracks may have different cross-sections — the unbalanced track case. This article briefly discusses the effect that track unbalance has on the value of the differential impedance.


How measured impedance may vary from field solver calculations when using woven glass reinforced laminates

Field solvers are in widespread use for calculation and analyzing controlled impedance structures. This note describes how, especially in fine geometry differential structures, differences of Er between the curing resin system and the woven glass reinforcement can result in differences between calculated and measured impedances.


Controlled Impedance design for test

This application note describes how implementing a few simple design considerations will assist fabricators achieve best yields and reduce the cost of high performance boards.


Sources of impedance measurement error

When measuring impedance with a Polar CITS or any other TDR there are a number of sources of potential measurement error. This application note sets out to explain those error sources and how you can minimise them in order to achieve repeatable and accurate measurements.


Characterising your process

The powerful math behind field solving tools which calculate impedance relies on the use of "ideal" materials. Unfortunately in the real world life is not quite as simple. This note briefly discusses characterising your process in order to achieve maximum yields.


Choosing the best probe for your application

When measuring impedance with a Polar CITS or any other TDR probe choice is important, this application note sets out to clarify which probe is ideal and clarify some of the misunderstandings that may exist.

IP Probe footprints (AP146)


Testing with Test Coupons

The accuracy of a controlled impedance trace on a PCB is usually critical to the correct performance of the PCB. This note describes some of the practical difficulties you'll sometimes run into when testing a controlled impedance PCB.

Sample coupon — Gerber Data mpcd1345.zip (170k)


CITS25 (End of life support) De-activation Procedure.

Support option information.


Test Procedure for Rambus® boards

This note describes the procedure for impedance measurement on the Rambus high speed memory architecture using the Polar Instruments CITS500s Controlled Impedance Test System.



Operating principle of groundless differential probes for CITS880s

Polar series of GDPS (groundless diferential) probes provides a measurement solution for situations where there is no physical access to the ground plane, or where a ground plane is not present. This note introduces the GDPS probe.


"Impedance modelling on multiple dielectric builds"

Gaudion, Martyn; Staniforth, J Alan - Circuit World; Volume 30 No. 2; 2004 © Emerald Group Publishing Limited 


This reprint from Circuit world magazine explains both the practice and theory behind modelling transmission lines on multiple dielectric PCB substrates


Critical length of transmission lines - Dr. Eric Bogatin

This new application note gives a clear and easy to read explanation of the critical length of a transmission line.  Written for Polar by Dr. Eric Bogatin this article is an ideal place to broaden your knowledge of PCB transmission line behaviour.  If you like this you will also find a broad range of PCB signal integrity related training materials on the Bogatin Enterprises website. www.bogent.com 


Paper Presented at IPC Expo 2002:

The Effect of Etch Taper, Prepreg and Resin Flow on the Value of the Differential Impedance

A Powerpoint presentation is also available (1.2Mb)

Free Powerpoint viewer


How field solvers such as the Si8000/9000 calculate impedance

Dr J Alan Staniforth

This application note provides a brief theoretical background to the impedance calculation methods used in the Polar Si series field solvers.


IPC Paper — "Calculation of PCB track impedance"

Andrew J Burkhardt, Christopher S Gregg & J Alan Staniforth

The use of high-speed circuits requires PCB tracks to be designed with controlled (characteristic, odd-mode, or differential) impedances.

For evaluating these impedances there are several well known published sources of equations that address a variety of configurations including stripline, surface microstrip, and their coplanar variants.

However, for some configurations there are differences between the equations given in these publications. The authors of this paper believe that it is now opportune to examine the origin of the equations and to update the method of calculation for use with modern personal computers.


Calculating differential and coplanar impedance on FR4

FR4 is a composite material, in most cases its a good approximation to assume a dielectric constant Er of 4.2. However, research into the prediction of impedance of edge coupled differential and coplanar structures has shown for the best results you need to take into account the composite structure of the material.


Paper — Calculating differential impedance on FR4 (pdf) (500k)

This paper discusses discrepancies between calculated and measured values of impedance for differential transmission lines on FR4 - especially noticeable in the case of surface microstrip configurations. The anomaly is shown to be due to the nature of the substrate material which needs to be considered as a layered structure of epoxy resin and glass fibre.

Calculations, using Boundary Element field methods, show that the distribution of the electric field within this layered structure determines the apparent dielectric constant and therefore affects the impedance. The paper shows that FR4 cannot be considered to be uniform dielectric when calculating differential impedance.


Effect of risetime on the TDR measurement of impedance

This application note is intended to give guidance to those making impedance measurements on industry standard 6 inch long coupons. The note will show that in this situation the use of risetimes shorter than 200ps will yield no advantage and in fact may prove more difficult to use.


Pictorial representation of the proximity effect of a ground plane

If PCB traces are routed closely together the signals on those traces can interfere with each other. This effect is known as crosstalk. The magnitude of the crosstalk on an adjacent trace is directly controlled by the interference of an adjacent electric field. Minimising the overlap of electric fields will reduce crosstalk and ensure maximum signal integrity.  This application note shows graphically how moving a trace closer to a plane helps reduce the area of influence of the electric field (more).



Installation and licensing support is now covered in the Installation section.


3D sensitivity analysis graphing on Si8000-Si9000

(PowerPoint presentation)

It is often useful to understand how different parameters interact for a controlled impedance structure. This brief note showcases the Sensitivity Analysis feature of the Si8000m and Si9000e field solvers, illustrating how multiple parameter variations in controlled impedance structures may be charted to provide instant detection of trends that are not easy to discover from a single result.


Graphing Z0 against Er

(PowerPoint presentation)

The Si8000 functions included in Excel format provide powerful analytical capabilities, allowing you to graph the effects of a range of parameter value changes. This tutorial explains how to change the axes of charts in Si8000 Excel workbooks so you can graph any variable you choose – Z0 against H, Z0 against Er, etc.

The tutorial assumes a basic working knowledge of Microsoft Excel.


Using the Polar Si8000 Excel Interface

(PowerPoint presentation)

The Si8000 Field Solver uses the familiar Microsoft Excel for Windows interface for easy graphing and data sharing. Using Excel’s powerful Autofill and Chart Wizard features, the Si8000 can rapidly chart Z0 against a varying parameter, providing easy comparison and evaluation of the behaviour of most popular controlled impedance structures. 
The tutorial assumes a basic working knowledge of Microsoft Excel.


Automating Si8000 goal seek with VBA

The Si8000 Goal Seek function is a powerful tool — given a controlled impedance structure's target impedance it can solve for track widths when other parameters (often dictated by manufacturing constraints) are provided.For some applications it's necessary to perform multiple "goal seeks" to achieve the final structure. In this note we use Excel's powerful macro language, Visual Basic for Applications (VBA) to construct a tapered transmission line structure. 


Transferring controlled impedance parameters between the SB200 and the Si8000

The SB200 incorporates the facility to add controlled impedance structures to a layer in the stackup. Structure parameters may be copied to the Si8000 Quick Solver for processing (for example by the Si8000 Goal Seeking function) and calculated values pasted back to the SB200 for insertion into the stackup.

This application note outlines the process of exchanging controlled impedance parameters between the SB200 and the Si8000 to add a controlled impedance structure with the correct impedance value to a stackup layer.


Updating Si8000m to interface with SB200a Professional Edition

The new SB200a Professional edition is designed to communicate and share layer stackup information with the Si8000m controlled impedance field solver. Together they form a powerful unified system for documentation and design of complex high speed PCB layer stackups and associated transmission line structures.

To realise communication between the two packages Si8000m existing customers need to update to Si8000 Version 3.00 or above.  Version 3.xx includes the links between the two products and supports some additional typical impedance controlled structures for multiple dielectric stackups.


Server and client side installation of the Si8000m floating license

This application note describes a simple FLEXLm server-side installation for both the Polar Si8000m and for Interface Module products that incorporate the Polar Impedance Calculation engine. 


Enhanced modelling of solder mask coatings with the Si8000m

This application note demonstrate how the modelling on the Polar Si8000 offers a significant enhancement over the Si6000 when trying to predict the finished impedance of surface microstrips.


Using coarse and fine convergence on the Si8000

The Si8000 field solver "goal seeks" for parameter dimensions on controlled impedance structures using an iterative calculation process. This note provides a worked example of using Si8000 coarse and fine convergence settings to model a structure.


Using the Si8000 field solver to model changes of thickness of LPI solder mask between traces

Printed circuit boards are often prototyped at a prototype/quick turn specialist shop before hand over to a volume plant. This note explains how impedance may be affected when the prototype shop and the volume fabricator deploy different soldermask application methods and describes how the Polar Instruments Si8000 Field Solver can be use to predict changes in the final impedance value of LPI coated differential traces due to non-uniform coating thickness.



Measuring instantaneous impedance with launch point extrapolation (LPE)

When working with narrow traces and thin copper your TDR impedance trace may show the effect of trace resistance as an upward slope. Polar's Atlas and CITS880s impedance test systems employ a technique to measure the instantaneous characteristic impedance of high frequency cables by removing the resistive elements through a technique called launch point extrapolation (LPE).


Calibration intervals for the CITS

How often should you calibrate your Controlled Impedance Test System? Some Polar CITS owners may be unsure how often they should calibrate the instrument; some even question the need for calibration at all. This note briefly discusses why Polar Instruments, in common with all reputable manufacturers of professional test equipment, recommends regular CITS maintenance and calibration. 


Protecting the CITS from electrostatic discharge

Sensitive electronic test equipment like the Polar Controlled Impedance Test Systems can prove vulnerable to damage from static electricity if proper anti-static procedures are not followed. This note looks at the best ways to prevent the build up of static charge in the work area — and avoid expensive repairs to your CITS.


Lossy traces - Where and how to use loss compensation on the CITS



Testing and modelling characteristic impedance of differential pairs without ground

This application note introduces Polar's groundless differential probes for testing balanced differential pairs where there are no reference planes and the Polar Si8000m and Si9000e field solver (v16.03 onwards) controlled impedance structures for modelling differentials without grounds.


IP Probe Footprints (Mechanical specification).



Setting impedance test limits so you  obtain accurate results and best R&R



Choosing the best probe for your application

IP Probe footprints ( AP146))


Measuring short traces



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